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5 projets européens trouvés

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 TERMINÉ 
NanoStreams co-designs a micro-server architecture and software stack that address the unique challenges of hybrid transactional-analytical workloads, which are encountered by emerging applications of real-time big-data analytics. To this end, NanoStreams brings together embedded system design principles, application-specific compilers, and HPC software practices.The processor technology that unde ...
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 7

 TERMINÉ 

Self adaptive heterogeneous manycore based on Flexible Tiles (FlexTiles)

Date du début: 15 oct. 2011, Date de fin: 14 avr. 2015,

Description To develop an energy-efficient programmable heterogeneous manycore platform with self-adaptive capabilities that apply to cognitive radio, video processing, embedded devices and ambient computingA major challenge in computing is to leverage multi-core technology to develop energy-efficient high performance systems. This is cri ...
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 12

 TERMINÉ 

A Highly Efficient Adaptive Multi-processor Framework (HEAP)

Date du début: 1 févr. 2010, Date de fin: 31 janv. 2013,

...pplications within a domain, huge performance and power improvements can be achieved by tailoring the cache architecture to the application at hand, and not just to an entire domain.The HEAP project faces these challenges directly, by developing:1. An innovative toolset that helps software developers profile and parallelize existing sequential implementations by exploiting top-level pipeline-style ...
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 11

 TERMINÉ 

Rendering FPGAs to Multi-Core Embedded Computing (REFLECT)

Date du début: 1 janv. 2010, Date de fin: 31 déc. 2012,

Description To develop an approach and a tool-chain to improve productivity by accelerating development cycles of reconfigurable systems by more than two orders of magnitude The ever increasing need for additional product functionalities, safety, and security, drives many product suppliers towards ...
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 10

 TERMINÉ 
Apple-CORE will develop compilers, operating systems and execution platforms to support and evaluate a novel architecture paradigm that can exploit many-core chips to the end of silicon. It adopts a systematic model of concurrency implemented as instructions in the processors' ISA (developed in the EU FP6 AETHER project). This has enormous potential but is disruptive, as this paradigm shift requir ...
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 6