As the probe size shrinks due to finer device pitches, its current carrying capability (CCC) is also reduced, conflicting with the future wafer test requirements for power delivery. Probe burn can result in damage to probe-card or pad of wafer tested, causing significant semiconductor wafer yield loss. The approach in the test industry has been mostly experimental for baseline data for determining this key parameter-CCC of probes on probe cards. Often, the CCC of a probe calculated empirically, does not agree well with measurements for dc and especially pulsed current applications. Accurate analytical models are needed for predicting probe CCC under both dc or pulsed current test loading for probes under compression. The main goal of the proposed research is to establish fundamental understanding of the probe burn phenomena through development of accurate models of probe current carrying capacity and verification of numerical and analytical models by data collected using a precise experimental measurement methodology. We will develop advanced analytical models representing electro-thermal characteristic of contacting probe and its environment by using advanced meshing techniques to perform simulations for any probe geometry. Time dependent algorithms to predict pulsed current loading will be included in the predictive tool. There will be special focus on cantilever or MEMS-type probes where the current restriction and probe burn happens on the probe tips. The software tool developed will be help users to optimize probe design and predict CCC limits accurately, thus prevent provide probe burn failures before wafer test. Another objective is to develop a cost-effective current limiter tool via thermistors mounted on a printed-circuit-board for advanced probe card technologies. This will be demonstrated using probe-cards for specific device power requirements.