Optical connectivity in data centers relies on 10Gb/s parallel optics that raise scalability and energy consumption issues. Efforts towards advanced modulation formats pose severe system complexity. The upgrade to 100 Gb/s to resolve the bandwidth bottleneck and increase the throughput of optical interconnect backplanes requires a disruptive yet straightforward solution. POLYSYS aims to provide this solution and realize 100Gb/s serial connectivity for rack-to-rack and chip-to-chip interconnects. POLYSYS will use electro-optic polymer as an integration platform where 100Gb/s modulators will be integrated monolithically, whereas InP lasers, detectors and electronics will be integrated hybridly. The InP-to-polymer integration technique will enable 95% coupling efficiency without using lenses and bulk optics. POLYSYS will fabricate the first serial 100Gb/s and 4x100Gb/s transmitters integrated with <1W-consuming electronic driver ICs, achieving 10 times higher line rates than mainstream 10 Gb/s VCSEL or silicon-based commercial products. POLYSYS will furthermore integrate 4x100Gb/s optoelectronic receivers monolithically in InP. The receivers will exhibit a high conversion gain to enable direct connectivity without optical amplifiers. The electronics will be integrated in arrays and the DEMUX circuit will demonstrate record low sensitivity. POLYSYS will demonstrate 4x100Gb/s direct data interconnection, increasing by 4 times the total throughput and reducing at least by a factor of 2 the required Energy/bit with respect to commercially available products. By demonstrating optical demultiplexing based on polymer, POLYSYS will show that the energy/bit can be further decreased by a factor of 5. Finally, POLYSYS will demonstrate serial 100Gb/s chip-to-chip interconnection by integrating transmitter and receiver at both ends of a polymer waveguide chip. As such POLYSYS will show compatibility with polymer backplanes and provide the technology for a tenfold capacity upgrade.