Scaling has driven the microelectronics industry for over 40 years and revolutionised information and communication technologies, health care, education, engineering, etc. Maintaining progress has becomes more challenging and costs of fabrication facilities are rising exponentially. Possible technical/cost solutions centre on development of ‘bottom-up’ techniques to (nano)pattern (the patterns yield device elements) surfaces rather than ‘top-down’ photolithographic (PL) methods that are the major cost of manufacturing circuitry (a single PL system is ~€65 million for next generation devices). Self-assembly is one route to nanopatterns but regularity/alignment over large areas is not consistent with circuit manufacture. Recent work on the self-assembly of block-copolymer (BCP) systems suggests that realisation of patterns of small feature size (~10 nm), at high density (i.e. spaced at ~10 nm), in precisely defined positions (to an accuracy of < 10 nm) on a large area substrate (12”) is possible. This proposal will develop BCP methodology into a set of process techniques for subsequent industrial pre-development. The methodology centres around a combination of bottom-up and top-down techniques to provide the fidelity required to make the methods reproducible and reliable. This proposal would have significant value:- - Enable continued development of devices towards their ultimate performance. - Allow development of advanced circuitry at lower costs. - Prevent monopolisation of the semiconductor industry by 1 or 2 companies that can afford capital costs by opening the market to new competition. - Afford the EU with opportunities to develop profitable companies in materials, process equipment and emerging device technologies. Without a suitable EU-level engagement in this area, competition in the US and Asia will gain a significant technological lead that will minimise the EU’s potential to deliver new and advanced nano-electronic devices.