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Energy Efficient Tunnel FET Switches and Circuits (E2SWITCH)
Date du début: 1 nov. 2013, Date de fin: 30 avr. 2017 PROJET  TERMINÉ 

E2SWITCH focuses on Tunnel FET (TFETs) as most promising energy efficient device candidates able to reduce the voltage supply of integrated circuits (ICs) below 0.25V and make them significantly more energy efficient by exploiting strained SiGe/Ge and III-V platforms, with CMOS technological compatibility. A full optimization and DC/AC benchmarking for complementary n- and p-type TFETs, integrated on the same fabrication platform, is proposed. Compact models are developed and implemented in Verilog A, for portability, to support the design of low power ICs with CMOS architectural compatibility for: (i) digital and (ii) analog/RF. The device scalability, operational reliability and the operation from room to high temperature, as required by ITRS metrics, are priorities of our investigations. In order to push even more the III-V and SiGe/Ge TFET performance we propose to study, optimize and experimentally validate new device concepts such as a Density-Of-State (DOS) switch exploiting the effect of dimensionality. The DOS switch will deliver deep subthermal switching (subthreshold swing less than 10mV/decade, for at least four decades of current).An advanced TCAD simulation platform is developed for the selected material systems, able to capture quantum effects and to accurately predict the influence of dimensionality. TCAD will also support the optimization of TFETs on the two proposed material platforms, with emphasis on the role of strain and on the alignment between the tunneling path and the electric field.A full set of characterization techniques including DC, AC, low frequency noise, RF measurements (S-parameters) and large range of temperature is foreseen to support the device optimization, parameter extraction and the calibration of the compact models.We will deliver very first full digital and analog circuit demonstrators and will benchmark their operational performance, reliability and robustness compared to equivalent CMOS technology nodes.



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