4 projets européens trouvés
Recherche sur 125080 projets européens
TERMINÉ
Semiconductor Equipment Assessment for Key Enabling Technologies (SEA4KET)
Date du début: 1 nov. 2013, Date de fin: 31 oct. 2016,
SEA4KET (Semiconductor Equipment Assessment for Key Enabling Technologies) is an IP proposal taking the consequent step from equipment R&D to equipment assessment experiments. The strategic objective is to effectively combine resources and expertise in a joint assessment of novel equipment for key enabling technologies to foster and accelerate the successful transfer of novel European equipment in ...
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26
Participants partenaires
TERMINÉ
Thermoplastically deformable circuits for embedded randomly shaped electronics (TERASEL)
Date du début: 1 oct. 2013, Date de fin: 30 sept. 2016,
The overall aim of the TERASEL project is the development, the industrial implementation and the application in a wide range of domains of large area, cost-effective, randomly shaped electronics and sensor circuit technologies. More specifically the TERASEL objectives are the following : To develop a basic technology platform for rigid large-area randomly shaped electronic circuits. Key common fe ...
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16
Participants partenaires
TERMINÉ
Silicon Quantum Wire Transistors (SQWIRE)
Date du début: 1 sept. 2010, Date de fin: 31 août 2013,
Description
SQWIRE develops industry compatible CMOS technology based on novel Si nanowire transistor structures.The aim of the SQWIRE project is to develop a disruptive, industry-compatible CMOS technology based on novel silicon nanowire transistor structures. As has been demonstrated both theoretically and experimentally, nanowire MOS t ...
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10
Participants partenaires
TERMINÉ
Dual-channel CMOS for (sub)-22 nm high performance logic (DUALLOGIC)
Date du début: 1 déc. 2007, Date de fin: 31 mai 2011,
We propose to develop for the first time a dual-channel CMOS technology comprising high channel mobility (high-µ) Ge pMOS and III-V compound semiconductor nMOS transistors co-integrated on the same complex engineered substrate on Si. This offers a high performance booster as an option for the 22 nm technology creating competitive advantage for the European nanoelectronics industry. In addition, hi ...
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