Co-design of HPC systems and applications

Date de clôture : 27 sept. 2016  
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Topic Description

Achieve world-class extreme scale, power-efficient and highly resilient HPC platforms through a strong co-design approach driven by ambitious applications and in close cooperation with the scientific disciplines and stakeholders concerned; achieve the full range of technological capabilities needed for delivering a broad spectrum of extreme scale HPC systems. The designs of these systems must respond to critical demands of energy efficiency, scale, resilience, programmability and support for various classes of applications including extreme-data applications.

Proposals with innovative and ground-breaking approaches to system architectures targeting extreme scale, power-efficient and highly resilient platforms with emphasis on balanced compute and data access characteristics. Special attention should be given to extreme data processing requirements. Proposals should have a strong co-design approach driven by a mix of ambitious applications and in close cooperation with the various scientific disciplines and stakeholders concerned. Proposals should show how their proposed solution improves energy efficiency and demonstrate the reduced energy-to-solution for the selected applications. Possible strategies for improving energy efficiency may include: reducing PUE (Power Usage Effectiveness), designing of cost-efficient approaches to the reuse of thermal energy, reducing the amount of energy spent for communication and data movement. Proposals should address the problem of maintaining reliability, coping with run-time errors and enabling stable operation of an HPC system that is able of extreme scaling; this issue may be addressed through holistic detection/recover approaches covering and orchestrating all layers of the HPC stack as well as significant advancements in fault prediction algorithms and smarter tools to prevent faults. Proposals should provide analytical or simulation models that allow to extrapolate the sustained performance on the given architecture for HPC systems. The target system architectures must scale to at least 100 PFlops and, for compute-centric workloads, a target of 15MW for 250 PFlops peak performance in 2019 is suggested. Proposals should explain how these scalability and energy-efficiency targets are achieved for the considered applications. APIs and interfaces between applications and underlying middleware, run-time and operating systems, i.e. all application-aspects impacting the underlying system design are included in this topic. Proposals should be able to demonstrate their achievements in integrated pre-exascale prototypes.

The Commission considers that proposals requesting a contribution between EUR 10 and 20 million would allow this specific challenge to be addressed appropriately. Nonetheless, this does not preclude submission and selection of proposals requesting other amounts.

• Contribution to the realisation of the ETP4HPC Strategic Research Agenda, thus strengthened European research and industrial leadership in HPC technologies.
• Proof-of-concept through integrated pre-exascale prototypes for future energy-efficient exascale-class HPC systems and optimal co-design driven by ambitious applications.
• Covering important segments of the broader and/or emerging HPC markets, especially extreme-scale HPC systems.
• Impact on standards bodies and other relevant international research programmes and frameworks.