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Topic 2 Focus topic on “High Performance RISC-V Automotive Processors supporting SDV”
Date de clôture : 17 sept. 2024  
- 199 jours

 Accélérateurs
 Entrepreneuriat et PME
 Recherche

Scope:

In automotive industry, being no exception from general CPS development trends, SW requirements and HW implementations change over time, which poses a need for an automated process to continuously evaluate different HW SoCs under changing SW requirements. The SDV paradigm provides an efficient mechanism to decouple HW from SW development while preserving system’s integrity and ensuring the propagation of functional and non-functional specifications across system’s abstraction layers. The key role for this decoupling of design concerns is attributed to the HAL in the SDV abstraction model. This focus topic assumes a collaborative agreement with representative European stakeholders on a reference HAL and targets an efficient hardware implementation of the latter based on RISC-V. Proposals need to particularly address but are not limited to the following hardware design aspects:

Sound tool-agnostic collaboration infrastructure based on joint APIs for automating the continuous assessment process and DSLs for iterating over different HW configurations. This infrastructure promotes and enables new flexible RISC-V based solutions for existing and new use-cases. The planned infrastructure will allow fast and seamless comparison to existing solutions in the different design phases.

Open high-performance RISC-V based automotive processor reference architecture, which can lead to customized instantiations towards specific automotive needs and control domains, including e.g. a superscalar architecture. It should also include a fast context switch with multi-threading support and fast deterministic interrupt/execution response.

Integrated vector unit(s) including custom extensions as e.g. DSP, AI, networking, etc. These should be scalable with chained registers and out-of-order execution.

Co-processor interface for special VPU and accelerators

Safety and security elements, extended to memory and interconnect. This should include spatial and temporal redundancy for temporary and permanent faults and ASIL certification. Security features should include secure enclave and potentially execution guard. Focus should also be on micro-architectural protection for side-channel attacks and SESIP certifications.

Exploration of different on-chip and off-chip interconnect solutions based on existing SotA (e.g. AMBA) or new developments (e.g. chiplets)

Virtualization support with Hypervisor.

Definition and adoption of standardised data formats, interfaces (APIs) and improved interoperability.

Mechanisms to capture and manage, from the software level, fuctional as well as non-functional characteristics of possible integration with SDV modules with particular focus on real-time operation, low power dissipation, handling of (precise) computational exceptions and interrupts.

Benchmarks and workloads for incremental hardware development. These must be usable on COTS HW, FPGA prototypes, simulators as well as emulators and must be also applicable for bare-metal and to top of full SW stacks, including hypervisors and RTOS. Multiple levels of incremental evaluations should be also supported. Finally, a trade-off between representativeness of the software and confidentiality constraints must be made.

Although the development of design software and tools is not a primary subject of this focus topic, efforts and resources needed to develop software enabling or facilitating the design of any of the essential elements of the hardware platform shall be eligible for funding

The consortium should be coordinated by a leading European industrial actor of the automotive industry value chain, or by a neutral organisation well established in the sector . The consortium must include: 

a representative number of European semiconductor companies with headquarters in several Member States; 

a representative number of European tier-1 automotive suppliers and technology companies with headquarters in several Member States;

a representative number of European OEMs of motorised vehicles (passenger cars, trucks, buses, motor cycles) with headquarters in several Member States; 

innovative SMEs across the value chain; 

universities and research and technology organisations bringing the newest advances in relevant digital and other technologies and/or acting act as neutral mediators. 

Proposals are encouraged:

To allocate tasks to cohesion activities with the projects selected under the call HORIZON-KDT-JU-2023-3-CSA Topic 3 on Coordination of the European software-defined vehicle platformon and the call HORIZON-KDT-JU-2023-2-RIA Topic 2 on Hardware abstraction layer for a European Vehicle Operating System.

To allocate tasks to cohesion activities with the projects selected under the previous calls HORIZON-KDT-JU-2021 and -2022 (TRISTAN & ISOLDE)

To allocate tasks to cohesion activities with the [call 2024 SDV].

To allocate tasks to cohesion activities with the [related CCAM and 2ZERO projects].



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